Field of the Invention
The present invention relates to an integrated memory chip with a dynamic memory.
Integrated memories for example in the form of so-called DRAM memories (dynamic random access memories) are operated in data processing systems and addressed by a microprocessor, for example. Above a certain size of the memory, for example in the case of a memory size in excess of 1 Mbit, all available DRAM memories generally use a so-called multiplex address scheme. The latter primarily serves for reducing the number of address terminals of a memory chip and thus the costs for the individual components in the data processing system and the power consumption of the corresponding address bus systems.
Such a multiplex address scheme has the advantage that it matches the functionality of a DRAM memory very well. In that case, there are generally activated for a memory access firstly the rows to be driven in the form of selected word lines and subsequently the corresponding columns in the form of selected bit lines. In the case of this address scheme, then, it is necessary to transmit firstly row addresses and subsequently corresponding column addresses. A selection is thus made as to the memory cells from which data are read or the memory cells to which data are written. The microprocessor must likewise send a plurality of individual commands, for example in the form of an activation signal, a read command or write command and, to conclude the memory access, a precharge command.
One disadvantage of such a functionality is, in particular, that a DRAM interface used for this purpose is generally not adapted to the corresponding processor interface. The processor interface is often adapted to fast so-called SRAM memories (synchronous RAM), which are very much smaller than DRAM memories and are generally not operated in the above-mentioned multiplex operating mode.
In order that such a processor interface and a DRAM interface can communicate with one another, it is generally necessary to implement a so-called DRAM controller in the data processing system in order to convert, in the data processing system, the DRAM-specific memory access from the commands of the processor which are oriented to SRAM memories.
It is accordingly an object of the invention to provide an integrated memory chip with a dynamic memory, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which makes it possible, in the case of use in a data processor system, to dispense with a DRAM controller.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory chip, comprising:
an external control terminal;
a dynamic memory;
a control circuit connected between the external control terminal and the dynamic memory for controlling a memory access to the dynamic memory;
the control circuit having an input connected to the external control terminal, for receiving an access command indicating a beginning of a memory access; and
the control circuit having an output connected to the dynamic memory, for outputting at least one signal generated from the access command and selected from the group consisting of an activation signal, a read command or write command, and a precharge command.
In other words, the objects of the invention are achieved with an integrated memory having an external control terminal, comprising a dynamic memory and a control circuit for controlling a memory access to the dynamic memory, having an input, which is connected to the external control terminal, for receiving an access command indicating the beginning of a memory access, and having an output, which is connected to the dynamic memory, for outputting at least one activation signal, read command or write command and precharge command generated from the access command.
The integrated memory chip according to the invention makes it possible to address the memory chip with the dynamic memory using a set of commands which is oriented to fast SRAM memories. The memory chip merely receives an access command, for example, from a connected processor, whereupon an activation signal, followed by a read command or write command and, finally, a precharge command are generated on-chip by the control circuit. This enables a situation where only an access command has to be transmitted between the memory chip and a connected microprocessor for a memory access. A DRAM controller separate from the memory chip does not have to be provided in a data processing system for addressing a DRAM memory.
The invention can be applied primarily to so-called RLDRAM memories, which have a high performance and storage capacity and are designed in particular for network applications. The invention therefore makes it possible to combine a very high storage capacity of a DRAM memory with optimized so-called random access times. This creates an alternative to fast SRAM to memories for operation in a data processing system, the SRAM memories having a much smaller memory size in comparison with DRAM memories.
In accordance with an added feature of the invention, the memory chip has an external address terminal, which is connected to an address terminal of the control circuit for receiving an address for the memory access, and the control circuit generates from a received address respective column addresses and row addresses for access to word lines and bit lines of the dynamic memory. This has the advantage that the DRAM-specific address generation with row addresses and column addresses is performed on-chip by the control circuit and so only one address has to be transmitted by the microprocessor.
In accordance with an additional feature of the invention, the memory chip has an external clock terminal for receiving an input clock for synchronized reading in of signals for the operation of the dynamic memory. In addition, the memory chip has an external terminal for a data reference signal, which is synchronized with output data to be output and which is derived from the input clock and is not synchronized with the latter. The memory chip thus has a terminal for a data reference signal which is like a so-called echo clock of an SRAM memory. However, the memory chip differs from a known DDR-DRAM memory, wherein a data reference signal is output in the form of a so-called data strobe signal. The generation of such a signal generally necessitates an additional so-called DLL circuit on the memory chip. Since the data reference signal of the memory chip according to the invention is derived from the input clock and is not synchronized with the latter, no DLL circuit is required in this case. In other words, the input clock and the data reference signal have a phase shift during operation of the memory chip.
The data reference signal serves, in particular, for controlling a memory access to the memory. In particular, the data reference signal indicates to an external functional unit the instant at which data to be read out are present at a data terminal. During a read access, the data reference signal is transmitted from the memory toward the outside together with data signals to be output and serves as reference signal of the data to be read out. In the memory according to the invention, the processing times of the data reference signal which is derived from the input clock (so-called clock tree) and the processing time of the output data to be output are synchronized with one another.
In accordance with a further feature of the invention, the memory chip has a plurality of external data terminals which are subdivided into at least two groups. Each of the groups is assigned to one of at least two terminals for a respective data reference signal, so that the assigned data reference signal is used as reference for data at the external data terminals of one of the groups. A so-called echo clock is thus provided for each group of data terminals, so that it can be ensured that a time shift between the echo clock signal and the output data of the DRAM memory is minimal. For individual groups of data terminals, the corresponding processing times are easier to synchronize with the data reference signal generated from the input clock.
In accordance with a concomitant feature of the invention, the dynamic memory has a memory cell array having bit lines and word lines, the memory chip has an external clock terminal for receiving an input clock, the control circuit is designed in such a way that, for a memory access, a plurality of individual actions to be performed from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with the input clock.
This makes it possible, in particular, to control the performance of a memory access with a clock signal which is made available for example by a synchronous circuit which communicates with the memory, in such a way that a high data throughput is made possible between the synchronous circuit and the dynamic memory. Since the individual actionsxe2x80x94to be performed for a memory accessxe2x80x94from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with the clock signal, so-called wait states can be avoided. In other words, the synchronous circuit does not have to wait for an unnecessarily long time for the processed data of the dynamic memory for further processing, since the memory access is synchronized with the clock signal.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory chip with a dynamic memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.